About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will help design, verify, and deploy ASIC projects through emulation based prototyping. You will work directly with other emulation Prototyping team members as well as Designers, Design Verification (DV) Engineers, Silicon Validation Engineers, and Software teams to deliver emulation based prototyping capabilities for our ASIC projects, including compiling projects managing our prototyping platforms, debugging issues in infrastructure and design, and assisting in the hardware and lab bring up and validation of our ASIC systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Responsibilities Build full chip emulation or FPGA prototypes from complex SoC designs and deliver to multiple customers such as Software, Firmware, Platform, and Post-Silicon Validation teams. Influence the Design and Verification teams to add emulation friendly model development. Bring up of system level emulation models through reset, boot, and bare metal content or OS. Work with Architects, Designers, Software Engineers, Pre and Post-Silicon Verification Engineers to develop test plans, coverage, and to reproduce failures on emulation. Develop, execute, and debug full-chip/System on a Chip (SoC) tests on emulation platforms. Explore new verification and emulation methodologies and implement them. Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug). Experience developing full-chip/SoC tests using the environments/tools (e.g., ASM, C, C++, Perspec, OS, or drivers). Experience with industry standard emulator technologies (e.g., HAPS, Zebu, Veloce, or Palladium) ranging from build tools to advanced capabilities (e.g. power aware emulation). Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., Xilinx, Altera). Preferred qualifications: Experience with EDA debug tools (e.g., Verdi, SimVision/Indago, GDB). Experience in programming and scripting in C, C++, Python, Perl, or TCL. Experience with AI usage for enhancing emulation flows and debug. Understanding of SoC architecture and interfaces (e.g., DDR, PCIe, etc.). Understanding of RTL to Emulation/FPGA flows including emulation test benches, DFT and virtual machines (e.g., transactors/accelerated VIPs, hybrid, in-circuit emulation).

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