ASIC DFT Engineer | DFT/ATPG/MBIST/SCAN/JTAG
Location
Bangalore / Hyderabad - India
Job Type
Full-Time
Experience Level
Senior Manager (5-7+ Years)
Salary Range
Not disclosed
Job Description
Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. You are an ASIC Design for Test Hardware Engineer with 8-10 years of related work experience with a broad mix of technologies. Minimum Qualifications: Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan insertion and ATPG. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Test Static Timing Analysis Post silicon validation using DFT patterns.
About Cisco
Cisco is the worldwide technology leader that is revolutionizing the way organizations connect and protect in the AI era. For more than 40 years, Cisco has securely connected the world. With its industry leading AI-powered solutions and services, Cisco enables its customers, partners and communities to unlock innovation, enhance productivity and strengthen digital resilience. With purpose at its core, Cisco remains committed to creating a more connected and inclusive future for all.
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Sai Charan
Senior Developer
Kalpana Sharma
Team Lead
Rahul Patel
Full Stack Developer
Priya Singh
Frontend Developer
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